High Speed Level Converters With Short Circuit Current Reduction

The level converter is used as interface between low voltages to high voltage boundary. The efficient level converter has less power consumption and less delay are the design considerations of the level shifter. In this paper two new CMOS level converters are presented with high driving capability with low propagation delay. The proposed level converters are simulated using Cadence software with 0.18 µm CMOS technology. The simulation result shows that the proposed circuits have less propagation delay than the existing ones. The circuits are simulated for different load capacitor values and different voltages. The proposed level converters operate for different input pulse signal amplitude values are +0.8 V, +1 V, +1.2 V and V DDH values of +1.8 V and +3.3 V .


I. INTRODUCTION
Transistor sizes in CMOS process technology lead to many advantages in terms of speed and functionality of the level converter [1]- [11].For maintaining reliability of system supply voltages come down when the size of the transistor is reduced.Level shifter is used in multi supply voltage systems where voltage difference problem exist.Level shifters are used in aero space systems, MEMS, power converters, and in microprocessors [12]- [21].
Conventional voltage level converter [2] is shown in Fig. 1.A low level voltage input signal V i is applied to the transistor T 1 and complementary input signal is applied to the transistor T 2 .The high level voltage output signals (V DDH ) are obtained at the node V op and V on .The input signal V i is high transistor T 1 is ON and T 2 is OFF then the node V op becomes High.V op node decreases from High (V DDH ) to Low when the input signal changing from High (V DDH ) to Low.Transistor T 1 has to sink the load discharge current and extra short circuit current from T 3 .The aspect ratios of PMOS transistors are larger than NMOS transistors because PMOS transistors have less transconductance.This requires large sized NMOS transistors to sink the PMOS current, it increases the short circuit currents.Short circuit currents increase the signal to noise ratio due to the impedance of supply rails.
The circuit presented in [3] is shown in Fig. 2. When the input V i and output V o both are low, then T 2 is ON.Input V i goes high, transistor T 3 cannot OFF instantly, because its source is connected to the voltage V DDH and gate terminal is connected to voltage V DDL .As a result transistor T 1 sinks the short circuit current from the transistor T 3 .Transistor T 2 acts as supply voltage switch for transistors T 3 and T 1 .T 2 acts as high resistance switch, hence the input at the gate of T 2 increases slowly.A sub threshold to the above threshold level converter [4] is shown in Fig. 3.This circuit has two stages.First stage uses the cross coupled inverter configuration with NMOS diode connected transistor on top.Second stage is the DCVS logic inverter used for achieving full swing.This design is not useful for high speed, because the second stage of this design affected by short circuit current problem.Second stage of the circuit is DCVSL inverter, the gate of one pull up transistor (T 7 ) is connected to drain of another pull up transistor (T 8 ), so short circuit current flows in the circuit when the pull up transistors (T 7 and T 8 ) are OFF.So propagation delay is increased because the circuit pulls down slowly.The circuit in [4] has higher delay values for 500 mV.This circuit is not used for external loads because it is self loaded.Another Level converter presented in [5] is shown in Fig. 4. Its speed increased than [4] by inserting PMOS diode connected transistors.The diode connected transistors T 3 and T 4 are used to limit the leakage current from pull up transistors T 1 and T 2 .This increases the speed of the circuit than Fig. 3.A voltage drop nearly equal to threshold voltage V th occurs in PMOS transistor T 3 or T 4 helps to quickly turn ON the PMOS transistor T 1 or T 2 when these are OFF.The diode drop reduces the output swing; to increase the swing additional transistors T 5 and T 8 are added to pull down the output to low voltage level.The diode connected transistors are used to limit the short circuit current and to improve the speed performance.To reduce the short circuit current further an additional feature is added in [6] hybrid level converter.In Fig. 5 [6] a technique is introduced to reduce the short circuit current.In this technique the PMOS latch is modified by adding resistors R 1 and R 2 .These resistances are replaced by NMOS transistors.Transistors T 5 and T 6 are used to minimize the short circuit current.Gate of each PMOS pull up transistor is separated by drain of other PMOS transistor with a resistance.The gate of PMOS transistor is pulled down by NMOS transistors T 5 and T 6 simultaneously.
Resistors block the short current from transistors T 1 and T 2 .Because of that PMOS transistors (T 1 and T 2 ) are pulled down quickly.Fig. 6.Conventional hybrid voltage level converter [6].
For achieving high speeds high resistance is useful.When the resistance is high it perfectly blocks the short circuit current from transistors T 1 and T 2 .The circuit presented in Fig. 6 [6] is implemented by combining resistive technique (Fig. 5) and diode technique (Fig. 4) in [5].The final circuit implementation is shown in Fig. 6.
When V op is high and V on is low in Fig. 6 the gate of the transistor T 1 is high where as T 1 is completely OFF.Hence T 11 has high resistance which helps to pull down the transistor T 1 .The gate of T 2 is connected to ground so T 12 has low resistance to pull up the transistor T 2 .Then the output V op become low and V on become high.In this state the gate of the transistor T 2 is high when T 2 is completely OFF.Hence T 12 has high resistance this is helped to pull down the transistor T 2 .The gate of T 1 is connected to ground so T 11 has low resistance to pull up the transistor T 2 .Then V op become high and V on become low.Transistors T 9 and T 10 are used to minimize the leakage current at pull up transistors T 1 and T 2 .

II. PROPOSED LEVEL CONVERTER CIRCUITS
In the proposed circuits the resistors implemented by using NMOS transistors shown in Fig. 6 [6] are replaced by PMOS transistors and diode connected transistors are also replaced by PMOS transistors used as resistors to quickly pull up the transistors T 1 and T 2 in proposed voltage level converter circuit-I.To block the short circuit current two methods are preferred.One method is to increase the aspect ratios of NMOS transistors T 11 and T 12 .Due to the increased aspect ratios of the NMOS transistors area and power consumption of the level converter are increased.Another method is to use the PMOS transistors as resistors.Because PMOS transistors have higher resistance compared to NMOS transistors.The resistance must be high for achieving lesser delay values.If the resistance is high the short circuit flows into the pull up transistors is blocked before the gate terminal and that short circuit current is minimized through the transistors T 7 and T 8 .The proposed level converter circuit-I is as shown in Fig. 7.When V op is high and V on is low in Fig. 7, the gate of the transistor T 1 is high whereas T 1 is completely OFF.Hence T 3 has high resistance this is helped to pull down the transistor T 1 .The gate of T 2 is connected to ground so T 4 has low resistance to pull up the transistor T 2 .Then the output V op becomes low and V on high.In this state the gate of the transistor T 2 is high, when T 2 is completely OFF.
Hence T 4 has high resistance this is helped to pull down the transistor T 2 .The gate of T 1 is connected to low voltage so T 3 has low resistance to pull up the transistor T 2 .Then V op become high and V on become low.Transistors T 7 and T 8 are used to minimize the leakage current at pull up transistors T 1 and T 2 .The input V ip is high where transistor T 2 and T 7 are ON.The short circuit current flowing from the transistor T 2 is minimized through T 7 .The input V ip is low then transistor T 1 and T 8 are ON.The short circuit current flowing from the transistor T 1 is minimized through T 8 .When the input voltage is in transition the operation of the circuit is explained in 3 regions.Region 1: In region 1 the input V ip is 0 ≤ V ip ≤ V DDL (where V DDL is the HIGH logic level applied at the input of the level converter) T 1 is ON and T 2 is OFF and a short circuit current flows from the transistor T 2 .Transistor T 3 blocks that short circuit current flowing from T 2 .If a small amount of short circuit current crosses the transistor T 3 then that is grounded through the transistor T 8 .Region 2: In region 2 the input V ip is equal to V DDL /2 all the PMOS and NMOS transistors are ON.No short circuit current flows from the PMOS pull up transistors because both the pull up transistors ON.The node V op raised from 0 to V DDH /2 and the V on falls from V DDH to V DDH /2.Region 3: In region 3 the input V ip is V DDL /2 ≤ V ip ≤ V DDL (where V DDL is the HIGH logic level applied at the input of the level converter) T 2 is ON and T 1 is OFF and a short circuit current flows from the transistor T 1 .Transistor T 4 blocks that short circuit current flowing from T 2 .If a small amount of short circuit current crosses the transistor T 4 then that is grounded through the transistor T 9 .
When short circuit current in the circuit is reduced the PMOS transistors quickly pulled down to LOW voltage level so response time of the output node V OP is increased.So delay of the circuit is reduced.T 11 and T 12 transistors are used as load helps to quickly turn ON the PMOS transistors.Transistors T 11 and T 12 are used to quickly pull up the output nodes V op and V on due to that raise time of the level converter is reduced.The proposed level converter circuit-II is as shown in Fig. 8.When V op is high and V on is low in Fig. 8 the gate of the transistor T 1 is high so T 1 is completely OFF.Hence T 3 has high resistance which helps to pull down the transistor T 1 .The gate of T 2 is connected to ground so T 4 has low resistance to pull up the transistor T 2 .Then the output V op become low and V on become high.In this state the gate of the transistor T 2 is high so T 2 is completely OFF.Hence T 4 has high resistance which helps to pull down the transistor T 2 .The gate of T 1 is connected to ground so that T 3 has low resistance to pull up the transistor T 2 .Then V op become high and V on become low.Transistors T 7 and T 8 are used to minimize the leakage current at pull up transistors T 1 and T 2 .When the input V ip is high then transistor T 2 and T 7 are ON.The short circuit current flowing from the transistor T 2 is minimized through T 7 .The input V ip is low then transistor T 1 and T 8 are ON.The short circuit current flowing from the transistor T 1 is minimized through T 8 .When the input signal is in transition the operation of the Fig. 8 is same as explained in the Fig. 7. T 5 and T 6 transistors are removed in Fig. 8 (proposed level converter circuit-II) to improve delay performance because a voltage drop V th exists in T 5 and T 6 due to that the transistors T 1 and T 2 in Fig. 7 are not completely OFF, so delay of the circuit is increased.When the transistors T 11 and T 12 in Fig. 8 are removed T 1 and T 2 takes more time to pull up then raise time is slightly increased and fall time is reduced because no voltage drop exist in Fig. 8.

III. SIMULATION RESULTS
The circuits are simulated for range of input pulse amplitudes of 0.8 V, 1 V and 1.2 V with the supply voltages of V DDH = 1.8 V and 3.3 V using gpdk 180 nm CMOS technology at a frequency of 5 KHz.The simulated input and output waveforms for Fig. 7 are shown in Fig. 9 and Fig. 13.And the simulated input and output waveforms for Fig. 8 are shown in Fig. 10 and Fig. 14.The simulated DC responses for Fig. 7 are shown in Fig. 11 and Fig. 15 and the simulated DC responses for Fig. 8 are shown in Fig. 12 and Fig. 16.The supply voltages are V DDH =1.8 V, 3.3 V and input pulse amplitude of 1 V.    Table III represents the comparison of simulated propagation delay values for proposed level converters with diodes based voltage level converter Fig. 4 and hybrid voltage level converter Fig. 6.In this table load capacitor values are varied from 2 pF to 25 pF, with input pulse amplitude of 1 V and frequency of 500 KHz.From table I it is clearly understand that there is a significant reduction of delay in the proposed level converters compared to existing circuits.Figure.17 and 18 represents propagation delay comparison of proposed level converters and conventional level converters for different input pulse amplitudes ranging from 0.6 V to 1.4 V with supply voltages V DDH =1.8 V and 3.3 V respectively.From Fig. 17 and 18 it is clearly understand that the proposed circuits have better speed performance than Fig. 4 and Fig. 6.When the input voltage amplitude is increasing speed performance of the circuit is increased.At lower supply voltages the speed of Fig. 4 and Fig. 6 is less compared with proposed circuits.Figure .19 and 20 represents propagation delay comparison of proposed level converters and conventional level converters for different loading conditions with supply voltages V DDH =1.8 V and 3.3 V respectively.When the load capacitor is increasing speed of the circuit is decreased.For V DDH of 3.3 V Fig. 4 shows better performance than Fig. 6.

Fig. 17 .
Fig. 17.Proposed level converters and conventional level converters propagation delay comparison for different input pulse amplitudes with supply voltage VDDH=1.8V.

Fig. 18 .
Fig. 18.Proposed level converters and conventional converters delay comparison for different input pulse amplitudes with supply voltage VDDH=3.3V.

Fig. 19 .
Fig. 19.Proposed level converters and conventional level converters propagation delay comparison for different loading conditions with supply voltage VDDH=1.8V.

Figure. 21
Figure.21 and 22 represents raise time comparison of proposed level converters and conventional level converters for different loading conditions with supply voltages V DDH =1.8 V and 3.3 V respectively.From Fig. 21 and 22 it is clearly understand that proposed circuit Fig. 7 has less raise times than Fig. 4, 6 and 8.When the load capacitor is increasing raise time of the circuit is increased.

Fig. 21 .
Fig. 21.Proposed level converters and conventional level converters raise time comparison for different loading conditions with supply voltage VDDH=1.8V.

Fig. 22 .
Fig. 22. Proposed level converters and conventional level converters raise time comparison for different loading conditions with supply voltage VDDH=3.3V.

Figure 23
Figure 23 and 24 represents fall time comparison of proposed level converters and conventional level converters for different loading conditions with supply voltages V DDH =1.8 V and 3.3 V respectively.From Fig. 23 and 24 it is clearly understand that proposed circuit Fig. 8 has less raise times than Fig. 4 and 6.When the load capacitor is increasing raise time of the circuit is increased.

Fig. 23 .
Fig. 23.Proposed level converters and conventional converters fall time comparison for loading conditions with VDDH=1.8V.

Fig. 24 .
Fig. 24.Proposed level converters and conventional level converters fall time comparison for different loading conditions with supply voltage VDDH=3.3V.

Table - I
represent the parameters of the pulse input applied at the input V ip of the level converters.Table-II represents the aspect ratios of the transistors used in the implementation of proposed level converters.

TABLE II .
ASPECT RATIOS

TABLE III .
COMPARISON OF SIMULATED PROPAGATION DELAY VALUES OF PROPOSED LEVEL CONVERTERS WITH EXISTING LEVEL CONVERTERS IN DIFFERENT LOAD CONDITIONS.

TABLE IV .
COMPARISON OF SIMULATED PROPAGATION DELAY, RAISE TIME AND FALL TIME VALUES OF PROPOSED LEVEL CONVERTER-I (FIG.7)

TABLE V .
COMPARISON OF SIMULATED PROPAGATION DELAY, RAISE TIME AND FALL TIME VALUES OF PROPOSED LEVEL CONVERTER-II (FIG.8)