High Speed Level Converters With Short Circuit Current Reduction

Avireni Srinivasulu, Adipudi Bala Tripura Sundari


The level converter is used as interface between low voltages to high voltage boundary. The efficient level converter has less power consumption and less delay are the design considerations of the level shifter. In this paper two new CMOS level converters are presented with high driving capability with low propagation delay. The proposed level converters are simulated using Cadence software with 0.18 µm CMOS technology. The simulation result shows that the proposed circuits have less propagation delay than the existing ones. The circuits are simulated for different load capacitor values and different voltages. The proposed level converters operate for different input pulse signal amplitudevalues are +0.8 V, +1 V, +1.2 V and VDDH values of +1.8 V and +3.3 V.

Full Text:



A.–J, Annema, B. Nauta, R. Van Langevelde and H. Tuinbout. “Analog circuits in ultra-deep-submicron CMOS”, IEEE Journal of Solid-States Circuits, vol.40, no.1, DOI: JSSC.2004.837247, 2005, pp.132-143.

D. Pan, Li, H. W. Wilamowski and B.M. “A low voltage to high voltage level shifter circuit For MEMS application”, in Proceedings of the 15th Biennial University/Government/IndustryMicroelectronics symposium, DOI: UGIM.2003.1225712, 2003, pp. 128-131.

Bo Zhang, Liping Liang, Xingiun Wang, “A new level shifter with low power in multi voltage system” In proceedings of 8th International Conference on Solid-State and Integrated Circuit Technology, DOI:ICSICT.2006.306488, 2006, pp.1857-1859.

S.N. Wooters, B. H. Calhoun, T. N. Blalock, “An Energy-efficient sub threshold level converter in 130nm CMOS”, IEEE Transactions on circuits and systems-II Express Briefs, Vol. 57, No. 4, DOI:TCSII.2010.2043471 April 2010, pp. 290-294.

H. Shao, C. Y. Tsui. “A robust input voltage adaptive and low energy consumption level converter for sub-threshold logic”, in Proc. of 33rd European Solid-State Circuits Conf. (ESSCIRC), DOI:ESSCIRC.2007.4430306, 2007, pp.312-315.

S. Ali, S. Tanner, P. A. Farine. “A robust, low power, high speed voltage level shifter with built-in short circuit current reduction”, in Proc. of 20th European Conf. on Circuit Theory and Design (ECCTD), DOI: ECCTD.2011.6043302, 2011, pp.142-145.

I. J. Chang, J. -J. Kim, Roy and K. , “Robust Level Converter Design for Sub-threshold Logic”, in Proc. of the International Symposium on Low Power Electronics and Design (ISLPED), DOI:LPE.2006.4271800, 2006, pp.14-19.

M. Vadipour, “A New compensation technique for resistive level shifters” IEEE Journal of Solid-State Circuits, vol.28, no.1, 1993, pp.93-95.

Y.Kanno, H.Mizuno, K.Tanaka, T.Watanabe, “Level converters with high immunity to power supply bouncing for high speed sub 1v VLSIs” In Proceedings of International Symposium on VLSI Circuits Digest of Technical papers, DOI:VLSIC.2000.852890, 2000, pp.202-203.

Wen-Tai Wang, Ming-Dou Ker, Mi-Chang Chiang, Chung-Hui Chen, “Level shifters for high speed 1V to 3.3V interfaces in a 0.13µm Cu-interconnection/low-k CMOS technology” In Proceedings of International Symposium on Technical Papers, DOI: VTSA.2001.934546, 2001, pp.307-310.

Mahendranath. B and Avireni Srinivasulu, “Analysis of two new voltage level converters with various load conditions,” International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems, vol. 2, no. 3, pp. 92-98, 2013. ISSN: 1805-5443.

J.Kim, M. H. Kim, S.L. Kim, C. K. Jeon, Y. S. Choi, H. S. Kang, C. S. Song, “The new high voltage level up shifter for HVIC” In proceedings of IEEE 33rd Annual Conference on Power Electronics Specialists, vol.2, DOI: PSEC.2002.1022523, 2002, pp.626-630.

C. Q. Tran, H. Kawaguchi, T. Sakurai, “Low power high speed level shifter design for block level dynamic voltage scaling environment” In proceedings of International Conference on Integrated Circuit Design and Technology, DOI:ICICDT.2005.1502637, 2005, pp.229-232.

Won-Ki Park, Cheol-Ung Cha, Sung-Chul Lee, “A Novel level shifter circuit design for display panel drivers” In Proceedings of 6th IEEE International Midwest Symposium on Circuits and Systems, vol.2, DOI:MWSCAS.2006.382294, 2006, pp.391-394.

J. F. da Rocha, M.B. dos Santos, J. M. Dores Costa, F. A. Lima, “Level shifter and DCVSL for a low voltage CMOS 4.2V buck converter” IEEE Transactions on Industrial Electronics, vol.55, no.9, DOI:TIE.2008.927974, 2008, pp.3315-3323.

J. Rocha, M. Santos, J. M. D. Costa, F. Lima “High voltage tolerant level shifters and DCVSL in standard low voltage CMOS technologies” In Proceedings of IEEE International Symposium on Industrial Electronics, DOI: ISIE.2007.4374695, 2007, pp.775-780.

J. C. Garcia, J. A. Montiel-Nelson, S. Nooshaadi, “High performance CMOS dual supply level shifter for a 0.5V input and 1V output in standard 1.2V 65nm technology process” In proceedings of 9th International Symposium on Communications and Information Technology, DOI: ISCIT. 2009. 5340988, 2009, pp.963-966.

J. C. Garcia, J. A. Montiel-Nelson, S. Nooshabadi, “High performance bootstrapped CMOS dual supply level shifter for 0.5V input and 1V output” In Proceedings of 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DOI: DSD.2009.180, 2009, pp.311-314.

Avireni Srinivasulu and M. Rajesh, “ULPD and CPTL pull-up stages for Differential Cascode Voltage Switch Logic,” Journal of Engineering (Hindawi), vol. 2013, Article ID 595296, 5 pages, 2013. ISSN: 2314-4912.

D. Wolpert, P. Ampadu, “Level shifter speed, power, and reliability trade-offs across normal and reverse temperature dependences” In Proceedings of 53rd IEEE International Midwest Symposium on Circuits and Systems, DOI: MWSCAS.2010.5548766, 2010, pp.1254-1257.

Y. Moghe, T. Lehmann, T. Piessens, “Nanosecond delay floating high voltage level shifters in a 0.35µm HV-CMOS technology” IEEE Journal of Solid-State Circuits, vol. 46, no. 2, DOI: JSSC.2010.2091322, 2010, pp.485-497.

DOI: http://dx.doi.org/10.11601/ijates.v3i2.92


  • There are currently no refbacks.